An example of PLL in the conventional technology is shown in FIG. 3. The PLL circuit in the example of FIG. 3 includes a phase comparator 10, a low pass filter 20, a voltage controlled oscillator (VCO) 30, forming a negative feedback loop.
A reference signal V1 and an oscillation frequency signal of the VCO 30 are provided to the phase comparator 10 wherein phases of two signals are compared and difference in the phase is detected. The phase difference signal V3 is provided to the low pass filter 20 which determines a loop response characteristics of the PLL. The low pass filter 20 smoothes the phase difference signal to convert the same to an error voltage or a control voltage which is supplied to the VCO 30 to control the oscillation frequency. When the PLL is in a lock-in situation, the phases, i.e., the frequencies of the oscillation signal V2 of the VCO 30 and the reference signal V1 match with one another.
PLL circuits are widely used in communication systems and devices, frequency synthesizers with a frequency divider therein, test instruments, signal generators, frequency modulators and the like.
In the conventional PLL circuit, an example of the phase comparator 10 is an analog multiplier such as a double balanced mixer. When a reference signal V1 and an oscillation signal V2 of the VCO 30 are expressed as equations (1) and (2), respectively, an output V3 of the phase comparator 10, which is an analog multiplier, is expressed by an equation (3) as follows. EQU V1=2.sup.1/2 A sin .theta.(t) (1) EQU V2=2.sup.1/2 B cos .theta.'(t) (2) EQU V3=AB sin (.theta.(t)-.theta.'(t))+AB cos (.theta.(t) +.theta.'(t))(3)
As shown in the right side of the equation (3), the output signal V3 of the phase comparator 10 includes a multiplied component showing a phase difference of the two signals V1 and V2 and a multiplied component showing a phase sum of the two signals V1 and V2. The output signal V3 is provided to the low pass filter 20 where the component having the phase sum of the two signals V1 and V2 is removed. Thus, the component (error voltage) showing the phase difference between the signals V1 and V2 is feed-backed to the VCO 30 to control the phase of the oscillation signal of the VCO 30.
Because the PLL circuit is a negative feedback loop, the PLL circuit functions to minimize the phase difference between the oscillation signal V2 and the reference signal V1. When the PLL circuit reaches the lock-in situation, the phases of the two signals match with one another, i.e., the oscillation frequency of the VCO 30 output signal V1 becomes the same as the frequency of the reference signal V2.
Parameters of the low pass filter 20 and a gain of the PLL circuit determine a response characteristics of the PLL circuit. In the operational process of the PLL circuit, there are two steps to reach the steady (phase lock) state of the PLL circuit. The first step is a frequency pulling process (pull-in) wherein the oscillation frequency of the VCO is driven close to the frequency of the reference signal. The second step is a phase synchronization (lock-in) process wherein the phases of the VCO output signal and the reference signal are completely synchronized.
In describing the operational ranges of a phase clock loop, such terms as a lock range, a pull-in range, and a lock-in range are generally used. The lock range means a maximum frequency difference between the VCO free running oscillation frequency and the reference signal frequency for which the PLL can maintain the lock-in state. The pull-in range (also called a capture range) means a frequency difference between the VCO free running oscillation frequency and the reference signal frequency for which the PLL can acquire the lock state. The lock-in range means a frequency difference between the VCO oscillation frequency and the reference signal frequency for which the PLL immediately goes into the lock state. The relationship among these ranges is that expressed as: EQU lock range&gt;pull-in range&gt;lock-in range (4)
The dynamic response characteristics of the phase lock loop is determined mainly by a transient response of the low pass filter 20. The parameters of the low pass filter 20 are selected so that the transient response shows, for example, a first order delay curve.
In case where the frequency difference between the oscillation frequency of the VCO 30 and the reference signal frequency is too large, frequency components in the difference signal from the phase comparator 10 may not pass through the low pass filter 20. This means that the frequency difference is outside of the pull-in range of the PLL, and thus, the lock state will not be achieved by the PLL circuit.
Once the PLL circuit establishes the lock state, the response speed of the PLL for following the frequency change in the reference signal, for example, is solely determined by the low pass filter 20. Since the low pass filter 20 has the delay response curve as noted above, when the PLL circuit is instantaneously out of the lock state by noise or the like, the lock state is immediately resumed. In other words, the low pass filter 20 performs as a memory for recording the control voltage to be supplied to the VCO 30 for a short period of time.
Generally, an SN (signal to noise) ratio, a pull-in range, a lock-in range, and a response speed of a phase lock loop are largely dependent upon a loop gain of the feed back loop of the PLL. When the loop gain increases, the pull-in range and the lock-in range increase as well while the time required for reaching the lock-in state decreases (loop response speed is high). However, the higher the loop gain, the lower it becomes the SN ratio, i.e., the noise increases. Conversely, when the loop gain decreases, the pull-in range and the lock-in range will decrease accordingly while the time required for reaching the lock-in state will increase (loop response speed is low). However, by the decrease of the loop gain, the SN ratio will improve, i.e., the noise decreases.
As in the foregoing, in the PLL circuit using the conventional phase comparator having the double balanced mixer or the like, the loop gain affects the PLL characteristics both advantageously and disadvantageously. Therefore, it is not possible to achieve all of the desired characteristics of a phase lock loop, i.e., a wide pull-in range and lock-in range, a high response speed, and a high SN ratio at the same time.